This invention relates to a buffer circuit, and more particularly to an address buffer circuit utilized for an MOS type dynamic RAM used for converting a signal at a bipolar logic level (transistor to transistor logic (TTL) level) into complementary signals at an MOS logic level.
FIG. 1a is a circuit diagram showing a prior art address buffer circuit which compares a reference potential with a TTL address input signal and converts the difference into complementary address signals at MOS levels.
In FIG. 1a, transistors 22 and 23 constitute a flip-flop circuit, and to a terminal VR is impressed a reference potential (an average value (about 1.5 V) of a permissible minimum value 2.2 V in a high (H) level region of a TTL input signal and a permissible maximum value in a low (L) level region). A high level TTL input signal is applied to an input terminal Ain which is adapted to receive an address input signal.
At first, it is assumed that the timing signals R.sub.1, R.sub.2, P.sub.1, P.sub.2 and P.sub.3 shown in FIG. 1b have levels H, H, L, L and L respectively. Then, transistors 1, 2 and 7 shown in FIG. 1a are turned ON so that capacitors 5 and 6 are charged to the level of the address input signal, while a capacitor 30 is charged to the reference potential. As a consequence thereof, transistor 20 and 21 are turned ON.
Transistors 11, 12, 13, 18 and 19 are also turned ON so that both output terminals Aout and Aout assume a ground potential, while nodes 9 and 10 are precharged to a potential of (V.sub.DD -V.sub.Ta) where V.sub.DD represents the source voltage of the MOS circuit, and V.sub.Ta represents the threshold values of transistors 11, 12 and 13.
Then, when the timing signals R.sub.1 and R.sub.2 change from an H level to an L level, and when the timing signals P.sub.1, P.sub.2 and P.sub.3 successively become an H level, a flip-flop circuit constituted by transistors 22 and 23 is latched such that the potential of a node 14 becomes (V.sub.DD -V.sub.Tb), whereas the potential of a node 15 becomes a ground potential, i.e., a low level due to the difference in the gate voltages of transistors 22 and 23, wherein V.sub.Tb represents the threshold value of transistor 16.
Accordingly, transistors 25 and 26 respectively become nonconductive and conductive so that a node 9 maintains the potential (V.sub.DD -V.sub.T) at the time of precharging, while a node 10 is at an L level or at a ground potential.
Since transistors 26 and 27 respectively become conductive and nonconductive, nodes 16 and 17 are respectively at an H level and at an L level . Consequently, transistor 28 is turned ON so that a signal at substantially an H level of the MOS voltage V.sub.Db appears at the output Aout. On the other hand, transistor 29 becomes nonconductive so as to produce a signal at an L level.
The address buffer circuit shown in FIG. 1a, however, has the following defects. Since it is necessary to use capacitor 5 for the purpose of preventing the misoperation of the transistor 21 due to an undershoot or overshoot of the address input signal, the time constant of the signal input unit becomes large, thus lengthening an address set up time.
Furthermore, when a TTL H level signal having the permissible minimum potential is applied, since the sensitivity of the flip-flop circuit becomes lower, the potentials of nodes 4 and 8 also become lower, thereby causing the misoperation of the flip-flop circuit. To prevent this difficulty, it is necessary to use capacitors 6 and 30 for compensating for the lowering of the node potentials by the timing signal P.sub.3.
Generally, it is difficult to set the compensating potential at an optimum value. Thus, where the compensation level of the nodes 4 and 8 is made too high, the time required for the timing signal P.sub.1 to latch the flip-flop circuit is lengthened and the currents flowing through transistors 16 and 20 are increased, thereby increasing the power consumption of the circuit.
Furthermore, the output terminals Aout and Aout, rather than outputting low level signals, float because of the fact that the gate electrodes of transistors 19 and 29 are at a low level, thus failing to positively produce low level outputs.
FIG. 2a shows another prior art address buffer circuit not using an exclusive reference source potential. In explaining the operation of the buffer circuit shown in FIG. 2a, it is assumed that a low level TTL input signal is applied to the address signal input Ain.
When timing signals R.sub.1, P.sub.1 and P.sub.2 shown in FIG. 2b have H, L and L levels respectively, transistors 32, 34, 35, 37, 38 and 40 become conductive with the result that nodes 45 and 48 assume a ground potential, whereas nodes 49, 44, 46 and 47 have potentials which are substantially equal to the source potential V.sub.DD.
Then, when timing signals R.sub.1, P.sub.1 and P.sub.2 become sequentially L, H and H levels, transistors 33 and 36 are rendered conductive while transistor 39 becomes conductive so that the potential of the node 47 becomes equal to a potential produced by dividing the source potential V.sub.DD with a capacitor 50 and the parasitic capacitance of a node 47. The gate electrode of transistor 39 is supplied with a potential obtained by dividing the source potential V.sub.DD with a capacitor 51 and a parasitic capacitance between the gate electrode of transistor 39 and ground. As a consequence thereof, transistor 39 becomes conductive so that the potential of the node 46 becomes equal to the ground potential and the logic levels of these nodes 46, 47 are transmitted to an output drive circuit 52.
However, in the address buffer circuit shown in FIG. 2a, when the address input signal is at a low level it is extremely difficult to design the capacitor 51 to have an optimum value sufficient to render the transistor fully conductive. When the capacitance of the capacitor 51 is made sufficiently large to make the gate voltage of the transistor 39 high, the speed of rendering the transistor 39 conductive becomes low when the address input signal is at a high level. Even when the optimum capacitance value for the capacitor 51 is selected, since such a capacitance is voltage dependent, as the source voltage V.sub.DD varies within a permissible range, the capacitance value would deviate from the optimum value.